----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:03:00 12/06/2011 
-- Design Name: 
-- Module Name:    top_gillis_green - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.game_logic_pkg.all;
use IEEE.NUMERIC_STD.ALL;

entity top_gillis_green is
	port( -- common inputs
			clk50 : in std_logic;
		   reset : in std_logic;
			
			-- signals for game logic
			row : in std_logic_vector(2 downto 0);
			col : in std_logic_vector(2 downto 0);
			play : in std_logic;
			
			--signals for vga controller 
			red : out  STD_LOGIC_VECTOR(2 downto 0);
			green : out  STD_LOGIC_VECTOR(2 downto 0);
			blue : out  STD_LOGIC_VECTOR(1 downto 0);
			hs : out  STD_LOGIC;
			vs : out  STD_LOGIC);			
end top_gillis_green;

architecture Behavioral of top_gillis_green is
	-- Components
	COMPONENT game_logic_top
		Port ( 
			clk50 : in  STD_LOGIC;
			reset : in  STD_LOGIC;
			game_board : out g_board;
			done : out std_logic;
			valid_move : out std_logic;
			player : out std_logic;
         play : in  STD_LOGIC;
         row : in  STD_LOGIC_VECTOR (2 downto 0);
         col : in  STD_LOGIC_VECTOR (2 downto 0));
	END COMPONENT;
	
	COMPONENT game_vga
		Port (
				clk50 : in  STD_LOGIC;
				reset : in std_logic;
				-- VGA output
				red : out  STD_LOGIC_VECTOR(2 downto 0);
				green : out  STD_LOGIC_VECTOR(2 downto 0);
				blue : out  STD_LOGIC_VECTOR(1 downto 0);
				hs : out  STD_LOGIC;
				vs : out  STD_LOGIC;
				-- Input from the game logic componenet
				game_board : in g_board;
				done : in std_logic;
				valid_move : in std_logic;
				player : in std_logic
				);
	END COMPONENT;		

	-- interconnect signals
	signal game_board : g_board;
	signal done : std_logic;
	signal valid_move : std_logic;
	signal player : std_logic;
	
	-- debouncer signals
	signal clk_en : std_logic;
	signal count : integer;
	signal play_out : std_logic;
	
begin
	-- quick debouncer
	-- Generate 1kHz Clock
	smallClock : process(clk50, reset)
	-- 1/2 of a full clock
	constant CLOCKCOUNTER : integer := 25000;
	-- Counter
	begin
		if(reset = '1') then
			count <= 0;
			clk_en <= '0';
		elsif (rising_edge(clk50)) then
			if count >= CLOCKCOUNTER then
				clk_en <= NOT(clk_en);
				count <= 0;
			else
				count <= count+1;
			end if;
		end if;
	end process;	
	
	buttonDebounce : process(clk50, reset)
	begin
		if(reset = '1') then
			play_out <= '0';
		elsif (rising_edge(clk50)) then
			if(clk_en = '1') then
				play_out <= play;			
			end if;
		end if;		
	end process;


	-- instantiation of game logic module
	U_game_logic_top : game_logic_top
		PORT MAP(
			clk50 => clk50,
			reset => reset,
			play => play_out,
			row => row,
			col => col,
			
			-- interconnect signals to vga block
			player => player,
			game_board => game_board,
			done => done,
			valid_move => valid_move);
		
	-- instantiation of VGA module
	U_game_vga : game_vga
		PORT MAP(
			clk50 => clk50,
			reset => reset,
			
			-- interconnect to vga output
			red => red,
			green => green,
			blue => blue,
			hs	=> hs,
			vs => vs,
			
			-- interconnect signals to vga block
			player => player,
			game_board => game_board,
			done => done,
			valid_move => valid_move);
			
			-- VGA DEBUG
--	done <= '1';
--	valid_move <= '0';
--	player <= '1';
--	process(clk50, reset) is
--	begin
--		if(reset = '1') then
--			game_board <= (others =>(others=>EMPTY));
--			game_board(6,3) <= BLACK;
--			game_board(7,2) <= WHITE;
--		elsif(rising_edge(clk50)) then
--		
--		end if;
--	end process;
			
			
			
end Behavioral;

